IC Design

 

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The 21st century technology is based on the Industrial Revolution 4.0 involving cyber-physical systems, the Internet of Things (IoT), and cloud-based computing. However, this technology would not be possible if the existing hardware systems cannot meet the demands of high processing power. The core fundamental design of these hardware systems are the internal design of integrated circuit (IC) such as the logic unit, control unit, processing unit and the memory unit. The process of designing these systems is called the Very Large-Scale Integration (VLSI) design.

The VLSI IC design is the fundamental to the microelectronics industry in the developed countries, which also includes the developing country such as Malaysia. Moreover, Malaysia is considered one of the leaders in this industry as the companies such as Intel, STMicroelectronics, Texas Instruments and other multi-national companies are located locally.

The establishment of the “IC Design” Focus Group (FG) in 2018 accelerates the generation and applications of new knowledge in designing the high-performance integrated circuits. It also promotes the knowledge transfer to FKEE students based on the concept of “Research to Practice”. The IC design related courses that are currently offered by FKEE are: (1) Digital Design, (2) Digital VLSI Design, (3) Analog VLSI Design, and (4) Computer Architecture.

Members

  1. Dr Chessda Uttraphan Eh Kan (› This email address is being protected from spambots. You need JavaScript enabled to view it.)

       Research interest: VLSI design automation, CNTFET, Digital logic design (Verilog HDL, VHDL), Embedded systems design (ARM)

  1. Professor Dr Abu Khari bin A’Ain (› This email address is being protected from spambots. You need JavaScript enabled to view it.)

        Research interest: Analog/RF IC design, IC test, Defect modelling

  1. Associate Professor Siti Hawa binti Ruslan (› This email address is being protected from spambots. You need JavaScript enabled to view it.)

        Research interest: Analog and digital IC design

  1. Dr Nabihah @ Nornabihah binti Ahmad (› This email address is being protected from spambots. You need JavaScript enabled to view it.)

        Research interest: Analog and digital IC design

  1. Dr Hasliza binti Hassan (› This email address is being protected from spambots. You need JavaScript enabled to view it.)

       Research interest: IC design, Fabrication and devices, Failure analysis, IC packaging

  1. Dr Chua King Lee (› This email address is being protected from spambots. You need JavaScript enabled to view it.)

       Research interest: Digital IC design, Embedded Systems

Research and Grants Awarded

  1. Fundamental Study of Agarwood Formation Detection with Non-destructive Magnetic Induction Mechanism – FRGS (2019-2020)
  2. Reconfigurable Architecture Development of Optical-based Distance Measurer – Short term (2017-2018)
  3. A 0.18 Um CMOS Ultra-Wide Band Low Noise Amplifier Based on Cascode Topology – GPPS (2018-2020)
  4. Reducing Power Consumption in The Design of CMOS ECG Bio-amplifier for Health Monitoring Purposes – FRGS (2017-2019)
  5. Design of Low Power High Speed CMOS Digital Multiplier Using Vedic Mathematics Method – GPPS (2016-2017)
  6. N-type-nanorods and Nanoflowers-Ti02/p-type Cu2O Heterojunction Thin Film Solar Cell – FRGS (2015-2018)
  7. An Improved Method for The Drain Current Estimation in Carbon Nanotube Field Effect Transistor – FRGS (2019-2021)
  8. An Improve Crosstalk Noise Model for Dynamic Programming Buffer Insertion Algorithm – TIER1 (2018-2020)
  9. Performance Enhancement for TFET Under Power Constraints Using DVFS – TIER1 (2018-2020)

Selected Publications

[1]     W. M. E. Aiman Bin Wan Jusoh and S. H. Ruslan, “Design of Low-Power Bulk-Driven Balanced OTA in 90nm CMOS Technology,” in IEEE 16th Student Conference on Research and Development, SCOReD, 2019, pp. 1–6.

[2]     W. M. E. A. B. W. Jusoh, S. H. Ruslan, N. Ahmad, W. M. Jubadi, and R. Sanudin, “Comparative study of symmetrical OTA performance in 180 nm, 130 nm and 90 nm CMOS technology,” Indones. J. Electr. Eng. Comput. Sci., vol. 14, no. 1, pp. 230–240, 2019.

[3]     F. Binti Noor Al Amin, N. Ahmad, and M. Hairol Jabbar, “A Low Power CMOS Phase Frequency Detector in High Frequency PLL System,” J. Phys. Conf. Ser., vol. 1049, no. 1, 2018.

[4]     L. S. Jie and S. H. Ruslan, “A 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology,” in AIP Conference Proceedings, 2017, vol. 1883, no. September 2017.

[5]     Z. Nasir and S. H. Ruslan, “A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module,” in IOP Conference Series: Materials Science and Engineering, 2017, vol. 226, no. 1.

[6]     L. S. Jie and S. H. Ruslan, “A 4x4 bit vedic multiplier with different voltage supply in 90 nm CMOS technology,” Int. J. Integr. Eng., vol. 9, no. 4, pp. 114–117, 2017.

[7]     W. M. E. A. W. Jusoh, C. C. Yee, S. H. Ruslan, and M. J. C. Soh, “Design of low power CMOS bioamplifier in 250 nm and 90 nm technology Node,” Int. J. Integr. Eng., vol. 9, no. 4, pp. 109–113, 2017.

[8]     N. Ahmad and Lim Yong Kang, “VLSI Implementation of Full Adder-Subtractor Design,” J. Eng. Appl. Sci., vol. 12, no. 14, pp. 3752–3757, 2017.

[9]     W. W. Kai, N. Ahmad, and M. H. Jabbar, “Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology,” Indones. J. Electr. Eng. Comput. Sci., vol. 14, no. 2, pp. 912–920, 2019.

[10]   A. Safuan Abu Naim and S. Hawa Ruslan, “130 nm Low Power CMOS Analog Multiplier,” J. Phys. Conf. Ser., vol. 1049, no. 1, 2018.

[11]   L. S. Jie and S. H. Ruslan, “A 2x2 bit multiplier using hybrid 13T full adder with Vedic mathematics method,” Int. J. Integr. Eng., vol. 10, no. 3, pp. 20–26, 2018.

[12]   N. Syuhadah Amran and S. Hawa Ruslan, “Low Power 130 nm CMOS Johnson Counter with Clock Gating Technique,” J. Phys. Conf. Ser., vol. 1049, no. 1, 2018.

[13]   N. Ahmad, M. Khairul Khalis Bin Ibrahim, and M. Hairol Jabbar, “Low Power Ultra-Wideband VCRO in 130nm CMOS Technology,” J. Phys. Conf. Ser., vol. 1049, no. 1, 2018.

[14]   B. Chan Jia Ching, A. A. H. Ab Rahman, and N. Ahmad, “Implementation of an 8x8 Discrete Cosine Transform on Programmable System-on-chip,” J. Phys. Conf. Ser., vol. 1049, no. 1, 2018.

[15]   N. Ahmad, N. Atikah Binti Ishaimi, and M. Hairol Jabbar, “Charge Pump and Loop Filter for Low Power PLL Using 130nm CMOS Technology,” J. Phys. Conf. Ser., vol. 1049, no. 1, pp. 0–10, 2018.

[16]   N. Ahmad, L. M. Wei, and M. Hairol Jabbar, “Advanced Encryption Standard with Galois Counter Mode using Field Programmable Gate Array.,” J. Phys. Conf. Ser., vol. 1019, no. 1, 2018.

[17]   C. Uttraphan, N. Shaikh-Husin, and M. Khalil-Hani, “An optimized buffer insertion algorithm with delay-power constraints for VLSI layouts,” Turkish J. Electr. Eng. Comput. Sci., vol. 25, no. 2, pp. 844–861, 2017.

[18]   C. Uttraphan, N. Shaikh-Husin, and M. Khalil-Hani, “Dynamic power dissipation formulation for application in dynamic programming buffer insertion algorithm,” J. Teknol., vol. 78, no. 11, 2016.

[19]   C. Uttraphan and N. Shaikh-Husin, “Hybrid routing tree with buffer insertion under obstacle constraints,” in Proceeding - 2013 IEEE Student Conference on Research and Development, SCOReD 2013, 2015.

[20]   C. Uttraphan and N. Shaikh-Husin, “An optimized algorithm for simultaneous routing and buffer insertion in multi-terminal nets,” ARPN J. Eng. Appl. Sci., vol. 10, no. 19, 2015.

[21]   C. Uttraphan, N. Shaikh-Husin, and M. K. Hani, “An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design,” in Proceedings - International Symposium on Quality Electronic Design, ISQED, 2014.

Activities

  1. Courses
  2. Industry Visit
  3. CSR
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For any inquiries, please contact us at:

Faculty of Electrical and Electronic Engineering (FKEE)
Universiti Tun Hussein Onn Malaysia (UTHM)
86400 Parit Raja, Batu Pahat
Johor, Malaysia

Tel: +607-4564505
Fax: +607-453 6337
Email: This email address is being protected from spambots. You need JavaScript enabled to view it.

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